1. Technical Field of the Invention
This invention relates to power gating. More particularly, it relates to power gating in CMOS chip architectures that incorporate voltage islands.
2. Background Art
Leakage currents are skyrocketing as CMOS technologies evolve from 130 nm to 90 nm and below. Chip architectures that incorporate voltage islands have become more commonplace as designers attempt to manage this leakage, particularly in power-sensitive applications.
If the magnitude of a voltage surge/droop due to ground bounce is greater than the noise margin of a circuit, the circuit may erroneously latch the wrong value or switch at the wrong time. Traditionally, ground bounce has been a phenomenon associated with input/output buffers and internal circuitry. In addition, ground bounce originating from the power-mode transition of a power gating structure affects the reliability of a system-on-a-chip (SOC) employing multiple power gating domains, or islands, to control leakage power. This noise source may induce ground bounce in neighboring circuits which are executing normal operations.
Leakage can be managed within voltage islands by reducing the supply voltages of non-switching islands (e.g., those clock gated off) or better yet, by powering such islands off altogether.
Since it is generally impractical to incorporate large numbers of independent power supplies in a system, schemes that allow the power supplies of multiple islands to be switched (or gated) on-chip are quite attractive. Such power gating typically places one or more large PFET devices, often called headers, between the chip VDD and island VDD supply rails. Alternatively, one or more large NFET devices, often called footers, may be placed between the chip GND and island GND supply rails. In either case, these power gating devices ideally function as low resistance switches when on (to minimize performance loss due to their insertion), yet provide high impedances (low leakage) to the supply rails when off.
The use of headers and footers can create additional design challenges. When a header or footer is switched from off to on, a significant increase in current may occur as island capacitances are charged. Similarly, if a header or footer is switched from on to off without previously gating off circuit switching activity, a significant decrease in current demand will occur. Large, fast changes in current demand can create substantial transient power supply noise (L×di/dt) in the chip power supply rails, which can adversely effect the performance or stability of operational circuits elsewhere on the chip.